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发表于 2020-11-30 16:38:24 4790 浏览 0 回复

LR13.R1.MP Gen93/Gen95 FeICIC/eICIC support

[Problem statement]: crs_InterfHandl-R11 and ss-CCH-InterfHandl-r11

[Solution]: MTK does not support both on Gen93 and Gen95. Gen 95 does not report as supported but implemented on R1.

For FeICIC, please make sure that the following items are enabled:

    SBP: SBP_LTE_FEICIC ->0x01 (this is default on @ LR13.R1)
    crs_interf_handl_r11 -> 0x01
    ss_CCH_interf_Handl_r11 -> 0x01

For eICIC, please make sure that the following items are enabled:

    SBP: SBP_LTE_FEICIC ->0x01 (this is default on @ LR13.R1)
    FGI bit 115 -> enabled

How to enable SBP for FeICIC

    Use NVRAM editor mode in META.
    read from NVRAM
    other--> NVRAM_EF_SBP_IDS_LID. Set 'test mode' as 8286(0x0000205e). Save to NVRAM.

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